1. Field of the Invention
The present invention relates to a semiconductor device including a VDMOSFET (vertical double diffused metal oxide semiconductor field effect transistor) of a trench gate type.
2. Description of Related Art
A VDMOSFET (hereinafter referred to as “VDMOS”) of a trench gate type is generally known as a power MOSFET having a lower on-resistance characteristic.
FIG. 9 is a schematic sectional view of a prior art semiconductor device including the VDMOS.
The semiconductor device 101 includes a semiconductor layer 102. The semiconductor layer 102 includes an N−-type drift region 103 and a P-type body region 104 disposed in this order from a bottom thereof.
The semiconductor layer 102 has a trench 105. The trench 105 extends through the body region 104 with its bottom located in the drift region 103. A gate insulation film 106 is provided on an interior surface of the trench 105. A gate electrode 107 is provided in the trench 105 with the intervention of the gate insulation film 106.
An N+-type source region 108 and a plurality of P+-type body contact regions 109 are provided in a surface of the body region 104.
A channel is formed in a portion of the body region 104 adjacent to an interface between the body region 104 and the gate insulation film 106 by controlling the potential (gate voltage) of the gate electrode 107 while grounding a source electrode (not shown) electrically connected to a source region 108 and applying a positive voltage to a drain electrode (not shown) electrically connected to the drift region 103. Thus, an electric current flows between the drift region 103 and the source region 108.
If a voltage higher than the rated voltage value of the VDMOS is applied between the source electrode and the drain electrode (between the source and the drain), the highest electric field intensity occurs around the bottom of the trench 105, so that avalanche breakdown occurs around the bottom of the trench 105. Holes generated by the avalanche breakdown flow into the body region 104, and migrate toward the source region 108 in the body region 104. However, draining of the holes from the body region 104 is liable to delay, because the body region 104 has a higher resistance. If a potential difference between the body region 104 and the source region 108 is increased to not lower than the on-voltage of a parasitic NPN transistor defined by the drift region 103, the body region 104 and the source region 108 due to the delay of the draining of the holes, the parasitic NPN transistor is turned on, thereby breaking down the VDMOS due to overcurrent.